1. Field of the Invention
The present invention relates to integrated circuit design, and more specifically, to a DC voltage generator for a system on chip (SOC).
2. Discussion of the Related Art
When designing and producing digital products, it is an ongoing goal to minimize size, increase capabilities and minimize power consumption. For example, the market calls for smaller and more powerful handheld digital products such as cellular phones, pagers, global positioning systems (GPS""s), personal digital assistants (PDAs), laptop computers and palm computers, while minimizing power consumption for extending battery life. To help accomplish this, System on Chip (SOC) design is implemented in which various components, such as volatile memory systems, non-volatile memory systems, data signal processing systems, mixed signal circuits and logic circuits are each formed into units and integrated on a single chip. Digital systems using SOC design, such as those used in handheld digital products, has replaced bulkier and higher power consuming digital systems built on a board in a package having several chips. As technology advances, integration of various units included in a SOC design becomes increasingly complicated.
The purpose of a DC voltage generator system on a semiconductor chip is to provide power regulation and power conversion, such as for converting a voltage provided by an external power supply, to a proper voltage level for performing an operation being executed by the chip. One particular challenge of integrating the various units is the provision of proper voltage levels to the individual units by an on-chip DC voltage generator system, as the units on the chip have a broad range of functionality as well as voltage and power requirements. For example, an embedded DRAM (eDRAM) unit generally requires a high operating voltage relative to digital logic circuit units, while analog circuits of mixed signal units generally require an even higher operating voltage. Regarding power requirements, memory units generally require less power than digital logic circuit units, while analog circuits of mixed signal units typically require more power than the other units.
A typical DC voltage generator system includes a central DC voltage generator having a plurality of regulator systems, and a pump system (also referred to as charge pump) associated with each regulator system. The DC voltage generator system further includes wiring for providing the voltages provided by the central DC voltage generator to the units of the chip. The DC voltage generator system having a central DC voltage generator is cumbersome, and is susceptible to contributing to power supply noise and noise cross-contamination between neighboring units.
FIG. 1 shows an exemplary conventional regulator system 30 of an on-chip DC voltage generator system, which is described in U.S. Pat. No. 6,060,873, to Ternullo, Jr. et al., which is incorporated herein by reference. The regulator system 30 receives a boosted supply voltage VH, a supply voltage VDD, and a power-up control signal PU, and outputs a boost control signal BC, which is propagated to a charge pump (not shown). The regulator system 30 is used to convert the externally supplied power to the voltage and current needed for the chip, while regulating the voltage with stability and noise reduction. The regulator system 30 controls the charge pump for increasing or decreasing the voltage output by the charge pump accordingly. The voltage output by the charge pump is provided to the various units of the chip.
A further disadvantage of the DC voltage generator system having a central DC voltage generator is that in order to provide enough current for full speed operation of the chip, in which one or more units operate in a high performance mode, the DC voltage generator system is usually designed to meet a highest power consumption condition. The charge pumps of the central DC voltage generator are controlled to all provide the same current to the units on the chip, even when one or more of the units on the chip are operating in a low-performance mode, thus wasting power.
Furthermore, the conventional DC voltage generator system having a central DC voltage generator does not generally contribute to power conservation. For example, in SOC design power conservation is implemented by using low power systems on chip (LP-SOC), which typically uses a low-power architecture. When operating in high performance mode, all units on an LP-SOC chip work at full speed. When switching activity is decreased, in which data processing speed and data input/output slows down and some units are disabled, the chip clock slows down in order to save power. However, the central DC voltage generator operates as usual by providing power to the units, regardless of whether the units are disabled or the chip clock output is changed, and power may be consumed without actually executing data.
Accordingly, a need exists for a system and a method for an SOC DC voltage generator system having a network of small sized distributed local voltage generators providing scalable voltage and power levels to different units on the chip. A need further exists for a system and method for an SOC DC voltage generator system that is controlled to operate in accordance with variable performance. Finally, a need exists for clock gated local voltage generators for individually controlling each local voltage generator in accordance with a clock signal indicative of a low performance mode.
It is an aspect of the present invention to provide a system and a method for an SOC DC voltage generator system having a network of distributed local voltage generators providing scalable voltage levels to different units on the chip.
It is a further aspect of the present invention to provide a system and method for an SOC DC voltage generator system that is controlled for operating in variable performance modes.
Finally, it is an aspect of the present invention to provide a system and method for clock gated local voltage generators for individually controlling each local voltage generator in accordance with a clock signal indicative of a low performance mode.
Accordingly, the present invention provides an SOC voltage generator system for supplying at least one voltage level to a plurality of units on a chip having an SOC design. The voltage generator system includes a plurality of local DC voltage generators distributed throughout the chip, each local DC voltage generator independently supplying voltage to at least one unit of the plurality of unites, each local DC voltage generator including a regulator system outputting one pump control signal; and a pump system receiving the one pump control signal and outputting at least one voltage level in accordance with the one pump control signal.
Furthermore, the present invention provides a method for supplying voltage to a plurality of units on a chip having an SOC design, the method including the steps of distributing a plurality of local DC voltage generators throughout the chip; and supplying at least one voltage level to the plurality of units via the plurality of local DC voltage generators.